1. Field of Invention
This invention relates to digital logic design, and more particularly, to methodologies for correcting design errors.
2. Description of Related Art
Modern digital logic devices offer unprecedented performance. For a variety of digital integrated circuits (IC""s), speed, level of integration (i.e. transistors per square centimeter) and capabilities have improved. Moreover, in many cases, these performance improvements have been accompanied by reductions in size, power consumption and cost of the devices. However, these benefits have required greater complexity in digital logic design. Because of this complexity, the investment of time and resources by the manufacturer to design and fabricate a digital logic device has increased. For this same reason, the possibility of a mistake or oversight on the part of the designer has become more likely, and costlier to correct.
Designers have dealt with this situation by incorporating spare logic elements in the digital logic device. The spare elements are not part of the functional circuitry, but are available to be xe2x80x9cpatched in,xe2x80x9d if necessary, to correct previously undetected design errors. While populating the IC with unused circuitry may appear inefficient, it is actually a prudent and economical practice. Design errors often go undiscovered until the IC is in an advanced stage of manufacturing, and the alternative to correcting these errors with spare gates is a (typically, quite expensive) complete re-design of the device.
As digital logic devices have continued to evolve, hierarchical design techniques have become valuable as an approach for managing their complexity. At each hierarchical level, logic elements are formed from combinations of simpler elements. At the lowest hierarchical level of the design, the elements include fundamental devices, such as gates and flip-flops. The top level of the design (often referred to as the xe2x80x9cparentxe2x80x9d) defines the interconnection of complex logic elements, each of which is made up of elements defined at lower levels. When elements are utilized at higher levels in a hierarchical design, their internal structure is not visiblexe2x80x94they are treated as xe2x80x9cblack boxesxe2x80x9d. The hierarchical approach thus simplifies the design process, since the designer must contend only with the complexity within a single hierarchical level. However, it raises a number of issues related to the correction of design errors, and to the optimum allocation and distribution of the spare gates, some of which are briefly discussed below.
The physical arrangement of the logic elements within an IC is referred to as the xe2x80x9clayout.xe2x80x9d When designing an IC, careful consideration must be given to layout, taking into account the effect of signal path lengths on timing, the possibility of interaction between adjacent signals, etc. Once it has been fully laid out, repair of a digital IC with a hierarchical design flow may be difficult or impractical. For example, if an additional signal is required to repair a module, it is generally not possible to simply route another input line to the module; instead, the layout of the module must be modified at a lower level in the hierarchy to include an additional input. If the affected module is used throughout the logic device, such a change can have a significant impact on the entire design.
A further consideration involving spare gates is that their use diminishes the fault testability of the design. Since, by definition, these gates are not part of any functional signal path, their inputs and outputs are not directly controllable or observable. Consequently, the presence of spare gates may limit the testability of the digital logic device.
Yet another concern is that in high-speed digital logic devices, the insertion of a spare gate into a signal path to correct a design error may have an adverse effect on critical device timing, depending on factors such as the resulting increase in path length, or the propagation delay through the spare gate.
An additional issue relates to the simulation of hierarchical digital logic designs. Before a digital logic design is fabricated into a physical device, the designer typically simulates the design. This involves the use of a sophisticated software model that predicts the behavior of the physical device. On the basis of the simulation, the designer may revise his design to correct errors or improve performance. Only after the results of the simulation are satisfactory, is the costly process of manufacturing a physical device begun. A difficulty arises with regard to the simulation of hierarchical designs, however. When spare gates are added to an original design, the length of time required for simulation naturally increases. If spare gates are widely used within a hierarchical design, the cumulative impact on simulation time may be severe.
Another concern applies to the power consumption attributed to the spare gates. Although these gates are not part of the functional circuitry, it is still possible for them to consume current and dissipate power. Therefore, if spare gates are included in a hierarchical digital logic design, it is desirable to employ some method to keep them in a low-power state.
Yet another consideration is the scalability of the spare gate collections used for repair. Generally, the functional modules within a hierarchical logic design vary in size and complexity. Thus, depending on the size of the functional module in which they are deployed, a greater or lesser number of spare gates may be needed. It is therefore desirable that the spare gates collections be readily scalable, commensurate with the size of the functional module in which they are included.
In view of the above considerations, it would be desirable to have a repair module consisting of spare gates. The repair module should be suitable for use in a hierarchical digital logic design. Therefore, it should permit the addition of input and output signals (if needed for repair) to a functional module without requiring a completely new layout. Furthermore, the desired repair module should not limit fault testability or adversely affect device timing. The repair module should also be scalable, so the number of spare gates available is commensurate with the complexity of the functional module being repaired. Unused spare gates within the repair module should not dissipate excessive power. In addition, the addition of multiple instances of the repair module should not adversely affect the time needed for software simulation of the parent design.
The problems outlined above are addressed by a system for allocating spare gates in the form of scalable repair modules having a fixed input/output layout and suitable for the repair of logic errors in a digital logic design with a hierarchical structure. Such a design is typically composed of independently created functional modules, referred to herein as xe2x80x9csubmacs.xe2x80x9d According to the system disclosed herein, each submac contains an appropriately-sized repair module, which is independent of the functional logic of the submac. These scalable repair modules consist of a number (depending on the size of the module) of identical sub-modules. The sub-modules are normally connected in series within their repair module, and at least some of the repair module inputs/outputs (I/O""s) are brought out as I/O""s of the submac. If repair becomes necessary, these xe2x80x9cextraxe2x80x9d I/O pins may be used to bring additional signals into or out of the submac.
One of the final steps in the process of fabricating a digital integrated circuit (IC) is metalization, in which a metallic pattern is deposited to interconnect the individual gates. Correcting a design error in a digital IC is simpler if it can be accomplished by altering the metalization pattern, thus changing the connections between existing components, than if it is necessary to actually add components or change their physical relationship. The sub-modules in the various embodiments of the system disclosed herein contain gates commonly required to repair design flaws. When utilized for such repairs, the sub-modules are effectively disassembled, making their constituent gates available to supplement the functional circuitry of the IC. By modifying the metalization pattern, the spare gates within the sub-modules are reconnected, incorporating them into the circuitry needing repair.
In an embodiment of the system disclosed herein, the majority of the spare gates within a sub-module are capable of being stimulated with a test signal, and their response to the test signal is capable of being measured. This is advantageous from the standpoint of fault coverage and testability of the IC. Furthermore, the sub-modules are configured to operate at very high clock speeds, preferably higher than that required for operation of the IC. In addition, the sub-modules receive both a clock signal and a reset signal. Sub-modules respond to a reset signal by assuming a stable state, wherein (in the absence of any input signal), an active clock signal will not produce logic transitions in any of the spare gates within the sub-module. Thus, unless they are being used for repair, spare gates do not contribute appreciably to power consumption in the IC.
Also disclosed herein, is a method for repairing logic errors in a digital logic IC. According to this method, spare gates are allocated in the form of identical sub-modules. Scalable repair modules are created by connecting a selectable number of sub-modules together in series, and these modules are distributed throughout the IC. If repair is necessary, the metalization layer interconnecting the components in the IC is modified so that some of the sub-modules are effectively disassembled and their spare gates incorporated into the circuitry portion in need of repair.
In an embodiment of this method, sub-modules not being used for repair are connected in series within their respective repair module, such that each sub-module in a series receives the output of the previous sub-module and drives the input of the next sub-module. Furthermore, the I/O""s of at least some of the sub-modules in a repair module are brought out as I/O""s of the repair module itself. These I/O""s provide a means of introducing additional signals (if required) for the repair of faulty circuitry within the IC, without the necessity of changing the physical layout to create new pins.